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1 ? fn7119.7 el5111, el5211, el5411 60mhz rail-to-rail input-output op amps the el5111, el5211, and el5411 are low power, high voltage rail-to-rail input-output amplifiers. the el5111 represents a single amplifier, the el5211 contains two amplifiers, and the el5411 contains four amplifiers. operating on supplies ranging from 5v to 15v, while consuming only 2.5ma per amplifier, the el5111, el5211, and el5411 have a bandwidth of 60mhz (-3db). they also provide common mode input ability beyond the supply rails, as well as rail-to-rail output capability. this enables these amplifiers to offer maximum dynamic range at any supply voltage. the el5111, el5211, and el5411 also feature fast slewing and settling times, as well as a high output drive capability of 65ma (sink and source). these features make these amplifiers ideal for high speed filtering and signal conditioning application. other applications include battery power, portable devices, and anywhere low power consumption is important. the el5111 is available in 5 ld tsot and 8 ld hmsop packages. the el5211 is available in the 8 ld hmsop package. the el5411 is available in space-saving 14 ld htssop packages. all featur e a standard operational amplifier pinout. these amplifie rs operate over a temperature range of -40c to +85c. features ? pb-free plus anneal available (rohs compliant) ? 60mhz (-3db) bandwidth ? supply voltage = 4.5v to 16.5v ? low supply current (per amplifier) = 2.5ma ? high slew rate = 75v/s ? unity-gain stable ? beyond the rails input capability ? rail-to-rail output swing ? 180ma output short current applications ? tft-lcd panels ?v com amplifiers ? drivers for a/d converters ? data acquisition ? video processing ? audio processing ? active filters ? test equipment ? battery-powered applications ? portable equipment pinouts el5111 (8 ld hmsop) top view nc vs+ vout nc vs- vin+ vin- nc 1 2 3 4 8 7 6 5 - + el5111 (5 ld tsot) top view 1 2 3 5 4 - + vin+ vs- vout vin- vs+ el5211 (8 ld hmsop) top view vs+ voutb vinb- vinb+ vs- vina+ vina- vouta 1 2 3 4 8 7 6 5 - + - + el5411 (14 ld htssop) top view - + - + - + - + vs- vs+ vinb+ vinb- voutb vina+ vina- vouta vinc+ vinc- voutc vind+ vind- voutd 1 2 3 4 14 13 12 11 5 6 7 10 9 8 data sheet may 7, 2007 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2004, 2007. all rights reserved all other trademarks mentioned are the property of their respective owners.
ordering information part number part marking tape & reel package p k g. d w g. # el5111iwt-t7 8 7? (3k pcs) 5 ld tsot mdp0049 EL5111IWT-T7A 8 7? (250 pcs) 5 ld tsot mdp0049 el5111iwtz-t7 (note) baag 7? (3k pcs) 5 ld tsot (pb-free) mdp0049 el5111iwtz-t7a (note) baag 7? (250 pcs) 5 ld tsot (pb-free) mdp0049 el5111iye 7 - 8 ld hmsop (3.0mm) mdp0050 el5111iye-t7 7 7? 8 ld hmsop (3.0mm) mdp0050 el5111iye-t13 7 13? 8 ld hmsop (3.0mm) mdp0050 el5111iyez (note) baaja - 8 ld hmsop (pb-free) (3.0mm) mdp0050 el5111iyez-t7 (note) baaja 7? 8 ld hmsop (pb-free) (3.0mm) mdp0050 el5111iyez-t13 (note) baaja 13? 8 ld hmsop (pb-free) (3.0mm) mdp0050 el5111aiyez (note) bblaa - 8 ld hmsop (pb-free) (3.0mm) mdp0050 el5111aiyez-t13 (note) bblaa 13? 8 ld hmsop (pb-free) (3.0mm) mdp0050 el5111aiyez-t7 (note) bblaa 7? 8 ld hmsop (pb-free) (3.0mm) mdp0050 el5211iye 9 - 8 ld hmsop (3.0mm) mdp0050 el5211iye-t7 9 7? 8 ld hmsop (3.0mm) mdp0050 el5211iye-t13 9 13? 8 ld hmsop (3.0mm) mdp0050 el5211iyez (note) baata - 8 ld hmsop (pb-free) (3.0mm) mdp0050 el5211iyez-t7 (note) baata 7? 8 ld hmsop (pb-free) (3.0mm) mdp0050 el5211iyez-t13 (note) baata 13? 8 ld hmsop (pb-free) (3.0mm) mdp0050 el5411ire 5411ire - 14 ld htssop (4.4mm) mdp0048 el5411ire-t7 5411ire 7? 14 ld htssop (4.4mm) mdp0048 el5411ire-t13 5411ire 13? 14 ld htssop (4.4mm) mdp0048 el5411irez (note) 5411irez - 14 ld htssop (pb-free) (4.4mm) mdp0048 el5411irez-t7 (note) 5411irez 7? 14 ld htssop (pb-free) (4.4mm) mdp0048 el5411irez-t13 (note) 5411irez 13? 14 ld htssop (pb-free) (4.4mm) mdp0048 el5411ir 5411ir - 14 ld tssop (4.4mm) mdp0044 el5411ir-t7 5411ir 7? 14 ld tssop (4.4mm) mdp0044 el5411ir-t13 5411ir 13? 14 ld tssop (4.4mm) mdp0044 el5411irz (note) 5411irz - 14 ld tssop (pb-free) (4.4mm) m14.173 el5411irz-t7 (note) 5411irz 7? 14 ld tssop (pb-free) (4.4mm) m14.173 el5411irz-t13 (note) 5411irz 13? 14 ld tssop (pb-free) (4.4mm) m14.173 note: intersil pb-free plus anneal products employ special pb-free mate rial sets; molding compounds/die attach materials and 100% mat te tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 2 fn7119.7 may 7, 2007 el5111, el5211, el5411
absolute maxi mum ratings (t a = +25c) thermal information supply voltage between v s + and v s - . . . . . . . . . . . . . . . . . . . .+18v input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . v s - - 0.5v, v s +0.5v maximum continuous output current . . . . . . . . . . . . . . . . . . . 65ma maximum die temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +150c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c ambient operating temperature . . . . . . . . . . . . . . . .-40c to +85c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 3 fn7119.7 may 7, 2007 important note: all parameters having min/max specifications are guaranteed. typ va lues are for information purposes only. unless otherwise not ed, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications v s + = +5v, v s - = -5v, r l = 1k to 0v, t a = +25c, unless otherwise specified parameter description conditions min typ max unit input characteristics v os input offset voltage v cm = 0v 3 15 mv tcv os average offset voltage drift (note 1) 7 v/c i b input bias current v cm = 0v 2 60 na r in input impedance 1 g c in input capacitance 2 pf cmir common-mode input range -5.5 +5.5 v cmrr common-mode rejection ratio for v in from -5.5v to 5.5v 50 70 db a vol open-loop gain -4.5v v out 4.5v 62 70 db output characteristics v ol output swing low i l = -5ma -4.92 -4.85 v v oh output swing high i l = 5ma 4.85 4.92 v i sc short-circuit current 180 ma i out output current 65 ma power supply performance psrr power supply rejection ratio v s is moved from 2.25v to 7.75v 60 80 db i s supply current no load (el5111) 2.5 4.5 ma no load (el5211) 5 7.5 ma no load (el5411) 10 15 ma dynamic performance sr slew rate (note 2) -4.0v v out 4.0v, 20% to 80% 75 v/s t s settling to +0.1% (a v = +1) (a v = +1), v o = 2v step 80 ns bw -3db bandwidth 60 mhz gbwp gain-bandwidth product 32 mhz pm phase margin 50 cs channel separation f = 5mhz (el5211 and el5411 only) 110 db d g differential gain (note 3) r f = r g = 1k and v out = 1.4v 0.17 % d p differential phase (note 3) r f = r g = 1k and v out = 1.4v 0.24 notes: 1. measured over operating temperature range. 2. slew rate is measured on rising and falling edges. 3. ntsc signal generator used. el5111, el5211, el5411
electrical specifications v s + = +5v, v s - = 0v, r l = 1k to 2.5v, t a = +25c, unless otherwise specified parameter description condition min typ max unit input characteristics v os input offset voltage v cm = 2.5v 3 15 mv tcv os average offset voltage drift (note 4) 7 v/c i b input bias current v cm = 2.5v 2 60 na r in input impedance 1 g c in input capacitance 2 pf cmir common-mode input range -0.5 +5.5 v cmrr common-mode rejection ratio for v in from -0.5v to 5.5v 45 66 db a vol open-loop gain 0.5v v out 4.5v 62 70 db output characteristics v ol output swing low i l = -5ma 80 150 mv v oh output swing high i l = 5ma 4.85 4.92 v i sc short-circuit current 180 ma i out output current 65 ma power supply performance psrr power supply rejection ratio v s is moved from 4.5v to 15.5v 60 80 db i s supply current no load (el5111) 2.5 4.5 ma no load (el5211) 5 7.5 ma no load (el5411) 10 15 ma dynamic performance sr slew rate (note 5) 1v v out 4v, 20% to 80% 75 v/s t s settling to +0.1% (a v = +1) (a v = +1), v o = 2v step 80 ns bw -3db bandwidth 60 mhz gbwp gain-bandwidth product 32 mhz pm phase margin 50 cs channel separation f = 5mhz (el5211 and el5411 only) 110 db d g differential gain (note 6) r f = r g = 1k and v out = 1.4v 0.17 % d p differential phase (note 6) r f = r g = 1k and v out = 1.4v 0.24 notes: 4. measured over operating temperature range. 5. slew rate is measured on rising and falling edges. 6. ntsc signal generator used. 4 fn7119.7 may 7, 2007 el5111, el5211, el5411
electrical specifications v s + = +15v, v s - = 0v, r l = 1k to 7.5v, t a = +25c, unless otherwise specified parameter description condition min typ max unit input characteristics v os input offset voltage v cm = 7.5v 3 15 mv tcv os average offset voltage drift (note 7) 7 v/c i b input bias current v cm = 7.5v 2 60 na r in input impedance 1 g c in input capacitance 2 pf cmir common-mode input range -0.5 +15.5 v cmrr common-mode rejection ratio for v in from -0.5v to 15.5v 53 72 db a vol open-loop gain 0.5v v out 14.5v 62 70 db output characteristics v ol output swing low i l = -5ma 80 150 mv v oh output swing high i l = 5ma 14.85 14.92 v i sc short-circuit current 180 ma i out output current 65 ma power supply performance psrr power supply rejection ratio v s is moved from 4.5v to 15.5v 60 80 db i s supply current no load (el5111) 2.5 4.5 ma no load (el5211) 5 7.5 ma no load (el5411) 10 15 ma dynamic performance sr slew rate (note 8) 1v v out 14v, 20% to 80% 75 v/s t s settling to +0.1% (a v = +1) (a v = +1), v o = 2v step 80 ns bw -3db bandwidth 60 mhz gbwp gain-bandwidth product 32 mhz pm phase margin 50 cs channel separation f = 5mhz (el5211 and el5411 only) 110 db d g differential gain (note 9) r f = r g = 1k and v out = 1.4v 0.16 % d p differential phase (note 9) r f = r g = 1k and v out = 1.4v 0.22 notes: 7. measured over operating temperature range 8. slew rate is measured on rising and falling edges 9. ntsc signal generator used 5 fn7119.7 may 7, 2007 el5111, el5211, el5411
6 fn7119.7 may 7, 2007 typical performance curves figure 1. 200 quantity (amplifiers) input offset voltage (mv) 0 -12 500 400 100 300 -10 -8 -6 -4 -2 -0 2 4 6 8 10 12 typical production distribution v s = 5v t a = +25c input offset voltage distribution figure 2. input offset voltage drift, tcv os (v/c) 1 3 5 7 9 11 13 15 17 19 21 5 quantity (amplifiers) 0 25 15 20 10 v s = 5v typical production distribution input offset voltage drift figure 3. 0.0 0.5 input offset voltage (mv) temperature (c) -0.5 1.0 -10 -50 30 70 110 150 1.5 2.0 input offset voltage vs temperature figure 4. 0.000 input bias current (a) temperature (c) -0.008 0.008 -0.004 -0.012 0.004 -50 -10 30 70 110 150 v s = 5v input bias current vs temperature figure 5. output high voltage vs temperature 4.88 4.90 output high voltage (v) 4.86 4.96 4.92 4.94 v s = 5v i out = 5ma temperature (c) -10 -50 30 70 110 150 figure 6. output low voltage vs temperature -4.91 -4.87 output low voltage (v) -4.95 -4.85 -4.89 -4.93 v s = 5v i out = 5ma temperature (c) -10 -50 30 70 110 150 el5111, el5211, el5411
7 fn7119.7 may 7, 2007 figure 7. 70 open-loop gain (db) 75 60 65 v s = 5v r l = 1k temperature (c) -10 -50 30 70 110 150 open-loop gain vs temperature figure 8. 75 76 slew rate (v/s) 74 78 73 72 77 v s = 5v temperature (c) -10 -50 30 70 110 150 slew rate vs temperature figure 9. 1.7 2.5 supply current (ma) supply voltage (v) 1.5 2.9 2.1 2.3 2.7 1.9 t a = +25c 8 4 121620 supply current per amplifier vs supply voltage figure 10. 2.45 2.50 supply current (ma) 2.40 2.60 2.65 2.55 2.70 v s = 5v temperature (c) -10 -50 30 70 110 150 supply current per amplifier vs temperature figure 11. -0.16 -0.04 differential gain (%) ire -0.18 0.00 -0.12 -0.06 -0.02 -0.14 0 100 200 -0.08 -0.10 v s = 5v a v = 2 r l = 1k differential gain figure 12. differential phase 0.20 differential phase () ire 0.00 0.30 0.15 0.25 0 100 200 0.10 0.05 typical performance curves (continued) el5111, el5211, el5411
8 fn7119.7 may 7, 2007 figure 13. -80 -40 distortion (db) v op-p (v) -90 -30 -60 -50 -70 2 04610 8 v s = 5v a v = 2 r l = 1k freq = 1mhz 3rd hd 2nd hd harmonic distortion vs v op-p figure 14. gain (db) 60 1k frequency (hz) phase () 40 20 250 190 130 70 10 -50 10k 100k 1m 10m 100m 80 0 -20 gain phase open loop gain and phase figure 15. magnitude (normalized) (db) 5 3 frequency (hz) 1 -1 -3 -5 100k 1m 100m 1k 10m 150 v s = 5v a v = 1 c load = 0pf 560 frequency response for various r l figure 16. magnitude (normalized) (db) frequency (hz) 25 15 5 -5 -15 -25 100k 1m 100m 10m 1000pf 100pf 47pf 10pf v s = 5v a v = 1 r l = 1k frequency response for various c l figure 17. output impedance ( ) 400 350 frequency (hz) 300 250 200 0 10k 100k 100m 1m 10m 150 100 50 closed loop output impedance figure 18. 2 10 maximum output swing (v p-p ) frequency (khz) 0 12 6 8 4 100k 10k 1m 100m 10m v s = 5v a v = 1 r l = 1k distortion <1% maximum output swing vs frequency typical performance curves (continued) el5111, el5211, el5411
9 fn7119.7 may 7, 2007 figure 19. cmrr (db) -15 frequency (hz) -45 -65 1k 10k 100m 1m 10m -55 100k -25 -35 cmrr figure 20. 0 psrr (db) -80 -60 -40 -20 psrr+ frequency (hz) 100 1k 10m 100k 1m 10k psrr- v s = 5v t a = +25c psrr figure 21. 10 100 voltage noise (nv/ hz) frequency (hz) 1 1k 100 1k 100m 1m 10m 100k 10k input voltage noise spectral density figure 22. -60 xtalk (db) -160 -120 -100 -80 dual measured ch a to b quad measured ch a to d or b to c other combinations yield improved rejection v s = 5v r l = 1k a v = 1 v in = 110mv rms -140 frequency (hz) 1k 10k 10m 30m 1m 100k channel separation figure 23. load capacitance (pf) overshoot (%) v s = 5v a v = 1 r l = 1k v in = 50mv t a = +25c 10 1k 100 100 0 40 60 80 20 small-signal overshoot vs load capacitance figure 24. -4 4 step size (v) settling time (ns) -5 5 0 2 -2 65 55 75 105 95 v s = 5v a v = 1 r l = 1k 85 3 -1 1 -3 0.1% 0.1% settling time vs step size typical performance curves (continued) el5111, el5211, el5411
10 fn7119.7 may 7, 2007 figure 25. 50ns/div 1v step v s = 5v t a = +25c a v = 1 r l = 1k large signal transient response figure 26. 50ns/div 100mv step v s = 5v t a = +25c a v = 1 r l = 1k small signal t ransient response pin descriptions el5111 (tsot-5) el5111 (hmsop8) el5211 (hmsop8) el5411 (htssop14) name function equivalent circuit 1 6 1 1 vouta amplifier a output v s+ gnd v s- circuit 1 4 2 2 2 vina- amplifier a inverting input v s+ v s- circuit 2 3 3 3 3 vina+ amplifier a non-inverting input (reference circuit 2) 5 7 8 4 vs+ positive power supply 5 5 vinb+ amplifier b non-inverting input (reference circuit 2) 6 6 vinb- amplifier b inverting input (reference circuit 2) 7 7 voutb amplifier b output (reference circuit 1) 8 voutc amplifier c output (reference circuit 1) 9 vinc- amplifier c inverting input (reference circuit 2) 10 vinc+ amplifier c non-inverting input (reference circuit 2) 2 4 4 11 vs- negative power supply 12 vind+ amplifier d non-inverting input (reference circuit 2) 13 vind- amplifier d inverting input (reference circuit 2) 14 voutd amplifier d output (reference circuit 1) 1, 5, 8 nc not connected typical performance curves (continued) el5111, el5211, el5411
11 fn7119.7 may 7, 2007 applications information product description the el5111, el5211, and el5411 voltage feedback amplifiers are fabricated using a high voltage cmos process. they exhibit rail-to-rail input and output capability, are unity gain stable and have low power consumption (2.5ma per amplifier). these features make the el5111, el5211, and el5411 ideal for a wide range of general- purpose applications. connected in voltage follower mode and driving a load of 1k , the el5111, el5211, and el5411 have a -3db bandwidth of 60mhz while maintaining a 75v/s slew rate. the el5111 is a single amplifier, the el5211 a dual amplifier, and the el5411 a quad amplifier. operating voltage, input, and output the el5111, el5211, and el5411 are specified with a single nominal supply voltage from 5v to 15v or a split supply with its total range from 5v to 15v. correct operation is guaranteed for a supply range of 4.5v to 16.5v. most el5111, el5211, and el5411 specifications are stable over both the full supply range and operating temperatures of -40c to +85c. parameter variations with operating voltage and/or temperature are shown in the typical performance curves. the input common-mode voltage range of the el5111, el5211, and el5411 extends 500mv beyond the supply rails. the output swings of the el5111, el5211, and el5411 typically extend to within 100mv of positive and negative supply rails with load currents of 5ma. decreasing load currents will extend the output voltage range even closer to the supply rails. figure 27 shows the input and output waveforms for the device in the unity-gain configuration. operation is from 5v supply with a 1k load connected to gnd. the input is a 10v p-p sinusoid. the output voltage is approximately 9.8v p-p . output input 5v 5v 10s v s = 5v, t a = +25c, a v = 1, v in = 10v p-p figure 27. operation with rail-to-rail input and output short circuit current limit the el5111, el5211, and el5411 will limit the short circuit current to 180ma if the output is directly shorted to the positive or the negative supply. if an output is shorted indefinitely, the power dissipation could easily increase such that the device may be damaged. maximum reliability is maintained if the output cont inuous current never exceeds 65ma. this limit is set by the design of the internal metal interconnects. output phase reversal the el5111, el5211, and el5411 are immune to phase reversal as long as the input voltage is limited from v s - -0.5v to v s + +0.5v. figure 28 shows a photo of the output of the device with the input voltage driven beyond the supply rails. although the device's output wil l not change phase, the input's overvoltage should be avoided. if an input voltage exceeds supply voltage by more than 0.6v, electrostatic protection diodes placed in th e input stage of the device begin to conduct and overvoltage damage could occur. 1v 1v 10s v s = 2.5v, t a = +25c, a v = 1, v in = 6v p-p figure 28. operation with beyond-the-rails input power dissipation with the high-output drive capability of the el5111, el5211, and el5411 amplifiers, it is possible to exceed the +125c 'absolute-maximum junction temperature' under certain load current conditions. therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the amplifier to remain in the safe operating area. the maximum power dissipation allowed in a package is determined according to: p dmax t jmax t amax ? ja -------------------------------------------- - = (eq. 1) where: ?t jmax = maximum junction temperature ?t amax = maximum ambient temperature ? ja = thermal resistance of the package ?p dmax = maximum power dissipation in the package el5111, el5211, el5411
12 fn7119.7 may 7, 2007 the maximum power dissipation actually produced by an ic is the total quiescent supply current times the total power supply voltage, plus the power in the ic due to the loads, or: p dmax iv [ s i smax v ( s +v out i ) i load i ? + ] = (eq. 2) when sourcing, and: p dmax iv [ s i smax v ( out iv s - ) i load i ? + ] = (eq. 3) when sinking, where: ? i = 1 to 2 for dual and 1 to 4 for quad ?v s = total supply voltage ?i smax = maximum supply current per amplifier ?v out i = maximum output voltage of the application ?i load i = load current if we set the two p dmax equations equal to each other, we can solve for r load i to avoid device overheat. figures 29 through 36 provide a convenient way to see if the device will overheat. the maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. by using t he previous equation, it is a simple matter to see if p dmax exceeds the device's power derating curves. to ensure proper operation, it is important to observe the recommended derating curves shown in figures 29 through 36 . figure 29. package power dissipation vs ambient temperature jedec jesd51-3 low effective thermal conductivity test board 0.9 0.8 0.6 0.4 0.3 0.2 0.1 0.0 0 255075100125 ambient temperature (c) power dissipation (w) 85 0.7 0.5 694mw ja = +144c/w htssop14 figure 30. package power dissipation vs ambient temperature jedec jesd51-7 high effective thermal conductivity (4-layer) test board - htssop exposed diepad soldered to pcb per jesd51-5 3.5 3.0 2.0 1.0 0.5 0.0 0 255075100125 ambient temperature (c) power dissipation (w) 85 2.632w 2.5 1.5 ja = +38c/w htssop14 jedec jesd51-3 low effective thermal conductivity test board 1.2 1.0 0.8 0.4 0.2 0.0 0255075100 150 ambient temperature (c) power dissipation (w) 1.042w 977mw 893mw ja = +140c/w tssop20 ja = +128c/w tssop24 ja = +120c/w tssop28 125 85 0.6 ja = +165c/w tssop14 ja = +148c/w tssop16 845mw 758mw figure 31. package power dissipation vs ambient temperature jedec jesd51-7 high effective thermal conductivity test board 1.8 1.6 1.2 0.6 0.4 0.0 0 25 50 75 100 150 ambient temperature (c) power dissipation (w) 1.667w 1.471w 1.389w ja =+90c/w tssop20 ja =+85c/w tssop24 ja =+75c/w tssop28 125 85 0.8 ja =+100c/w tssop14 ja =+97c/w tssop16 1.289w 1.250w 1.4 1.0 0.2 figure 32. package power dissipation vs ambient temperature el5111, el5211, el5411
jedec jesd51-3 low effective thermal conductivity (single layer) test board power dissipation (w) 0.300 0.250 0.200 0.150 0.100 0.050 0.000 0.350 ambient temperature (c) 0 25 50 75 100 125 85 150 290mw tsot5 ja = +345c/w figure 33. package power dissipation vs ambient temperature package power dissipation vs ambient temperature figure 34. 0.6 0.5 0.4 0.3 0.2 0.1 0.0 jedec jesd51-7 high effective thermal conductivity (4-layer) test board 483mw tsot5 ambient temperature (c) power dissipation (w) 0 25 50 75 100 125 85 150 ja = +207c/w jedec jesd51-3 low effective thermal conductivity test board 0.6 0.4 0.3 0.2 0.1 0 0 25 50 75 100 125 ambient temperature (c) power dissipation (w) 85 486mw j a = + 2 0 6 c / w h m s o p 8 0.5 figure 35. package power dissipation vs ambient temperature figure 36. jedec jesd51-7 high effective thermal conductivity test board 1 0.9 0.6 0.4 0.3 0.2 0.1 0 0 25 50 75 100 125 ambient temperature (c) power dissipation (w) 85 870mw j a = + 1 1 5 c / w h m s o p 8 0.8 0.5 0.7 package power dissipation vs ambient temperature 13 fn7119.7 may 7, 2007 unused amplifiers it is recommended that any unused amplifiers in a dual and a quad package be configured as a unity gain follower. the inverting input should be direct ly connected to the output and the non-inverting input tied to the ground plane. power supply bypassing and printed circuit board layout the el5111, el5211, and el5411 can provide gain at high frequency. as with any high-frequency device, good printed circuit board layout is necessary for optimum performance. ground plane construction is highly recommended, lead lengths should be as short as possible and the power supply pins must be well bypassed to reduce the risk of oscillation. for normal single supply operation, where the v s - pin is connected to ground, a 0.1f ceramic capacitor should be placed from v s + to pin to v s - pin. a 4.7f tantalum capacitor should then be connected in parallel, placed in the region of the amplifie r. one 4.7f capacitor may be used for multiple devices. this same capacitor combination should be placed at each supply pin to gr ound if split supplies are to be used. el5111, el5211, el5411
14 fn7119.7 may 7, 2007 el5111, el5211, el5411 thin shrink small outline package family (tssop) n (n/2)+1 (n/2) top view a d 0.20 c 2x b a n/2 lead tips b e1 e 0.25 cab m 1 h pin #1 i.d. 0.05 e c 0.10 c n leads side view 0.10 cab m b c see detail ?x? end view detail x a2 0 - 8 gauge plane 0.25 l a1 a l1 seating plane mdp0044 thin shrink small outline package family symbol millimeters tolerance 14 ld 16 ld 20 ld 24 ld 28 ld a 1.20 1.20 1.20 1.20 1.20 max a1 0.10 0.10 0.10 0.10 0.10 0.05 a2 0.90 0.90 0.90 0.90 0.90 0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 d 5.00 5.00 6.50 7.80 9.70 0.10 e 6.40 6.40 6.40 6.40 6.40 basic e1 4.40 4.40 4.40 4.40 4.40 0.10 e 0.65 0.65 0.65 0.65 0.65 basic l 0.60 0.60 0.60 0.60 0.60 0.15 l1 1.00 1.00 1.00 1.00 1.00 reference rev. f 2/07 notes: 1. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. dimension ?e1? does not incl ude interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm per side. 3. dimensions ?d? and ?e1? are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m - 1994.
15 fn7119.7 may 7, 2007 el5111, el5211, el5411 htssop (heat-sink tssop) family n (n/2)+1 (n/2) top view a d 0.20 c 2x b a n/2 lead tips b e1 e 0.25 cab m 1 h pin #1 i.d. 0.05 e c 0.10 c n leads side view 0.10 cab m b c see detail ?x? end view detail x a2 0 - 8 gauge plane 0.25 l a1 a l1 seating plane bottom view exposed thermal pad e2 d1 mdp0048 htssop (heat-sink tssop) family symbol millimeters tolerance 14 ld 20 ld 24 ld 28 ld 38 ld a 1.20 1.20 1.20 1.20 1.20 max a1 0.075 0.075 0.075 0.075 0.075 0.075 a2 0.90 0.90 0.90 0.90 0.90 +0.15/-0.10 b 0.25 0.25 0.25 0.25 0.22 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 d 5.00 6.50 7.80 9.70 9.70 0.10 d1 3.2 4.2 4.3 5.0 7.25 reference e 6.40 6.40 6.40 6.40 6.40 basic e1 4.40 4.40 4.40 4.40 4.40 0.10 e2 3.0 3.0 3.0 3.0 3.0 reference e 0.65 0.65 0.65 0.65 0.50 basic l 0.60 0.60 0.60 0.60 0.60 0.15 l1 1.00 1.00 1.00 1.00 1.00 reference n 1420242838reference rev. 3 2/07 notes: 1. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. dimension ?e1? does not incl ude interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm per side. 3. dimensions ?d? and ?e1? are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m - 1994.
16 fn7119.7 may 7, 2007 el5111, el5211, el5411 tsot package family e1 n a d e 4 (n/2) 2 1 e1 0.15 d c 2x 0.25 c 2x n/2 tips e b ddd m d c a-b b nx 6 2 3 5 seating plane 0.10 c nx 1 3 c d 0.15 a-b c 2x a2 a1 h c (l1) l 0.25 4 4 gauge plane a mdp0049 tsot package family symbol millimeters tolerance tsot5 tsot6 tsot8 a 1.00 1.00 1.00 max a1 0.05 0.05 0.05 0.05 a2 0.87 0.87 0.87 0.03 b 0.38 0.38 0.29 0.07 c 0.127 0.127 0.127 +0.07/-0.007 d 2.90 2.90 2.90 basic e 2.80 2.80 2.80 basic e1 1.60 1.60 1.60 basic e 0.95 0.95 0.65 basic e1 1.90 1.90 1.95 basic l 0.40 0.40 0.40 0.10 l1 0.60 0.60 0.60 reference ddd 0.20 0.20 0.13 - n 5 6 8 reference rev. b 2/07 notes: 1. plastic or metal protrusions of 0.15mm maximum per side are not included. 2. plastic interlead protrusions of 0.15mm maximum per side are not included. 3. this dimension is measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m-1994. 5. index area - pin #1 i.d. will be located within the indicated zone (tsot6 and tsot8 only). 6. tsot5 version has no center lead (shown as a dashed line).
17 fn7119.7 may 7, 2007 el5111, el5211, el5411 hmsop (heat-sink msop) package family 1 (n/2) (n/2)+1 n plane seating n leads 0.10 c pin #1 i.d. e1 e b detail x 3 3 gauge plane see detail "x" c a 0.25 a2 a1 l 0.25 c a b d a m b e c 0.08 c a b m h l1 end view side view top view e2 bottom view d1 exposed thermal pad mdp0050 hmsop (heat-sink msop) package family symbol millimeters tolerance notes hmsop8 hmsop10 a1.001.00 max. - a1 0.075 0.075 +0.025/-0.050 - a2 0.86 0.86 0.09 - b 0.30 0.20 +0.07/-0.08 - c0.150.15 0.05 - d 3.00 3.00 0.10 1, 3 d1 1.85 1.85 reference - e4.904.90 0.15 - e1 3.00 3.00 0.10 2, 3 e2 1.73 1.73 reference - e0.650.50 basic - l0.550.55 0.15 - l1 0.95 0.95 basic - n 8 10 reference - rev. 1 2/07 notes: 1. plastic or metal protrusions of 0.15mm maximum per side are not included. 2. plastic interlead protrusions of 0.25mm maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m-1994.
18 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7119.7 may 7, 2007 el5111, el5211, el5411 thin shrink small outlin e plastic packages (tssop) d index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. these package dimensions are within allowable dimensions of jedec mo-153-ac, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include interlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimen- sion at maximum material conditi on. minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millime ter. converted inch dimensions are not necessarily exact. (angles in degrees) 0.05(0.002) m14.173 14 lead thin shrink small outline plastic package symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.002 0.006 0.05 0.15 - a2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - d 0.195 0.199 4.95 5.05 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n14 147 d 0 o 8 o 0 o 8 o - rev. 2 4/06

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